1. Field of the Invention
The present invention relates to a semiconductor fabricating method. More particularly, the present invention relates to a method of fabricating, a mixed-mode device.
2. Description of the Related Art
A mixed-mode device is frequently utilized in an embedded dynamic random access memory (DRAM) or an embedded static random access memory (SRAM). In a mixed mode device, different gates are supplied with different operation voltages. For example when the gate lengths are 0.25 micro-meter 0.3 micro-meter, and 0.5 micro-meter, the current and operation voltages for the gate are 50 A/2.5 V. 70 A/3.3 V, and 130 A/5 V, respectively.
A dual-gatc oxide layer is required in a mixed-mode device. A dual-gate oxide layer includes a thick gate oxide layer and a thin gate oxide layer. The thick gate oxide layer is formed by double oxidation steps and the thin gate oxide layer is formed by single oxidation step. The thick gate oxide layer and the thin gate oxide layer are formed on different side of an isolation structure. Then, some follow-up steps are performed to complete a mixed-mode device.
FIGS. 1A through 1D are schematic, cross-sectional views showing a fabricating process for a conventional mixed-mode device.
In FIG. 1A, an isolation structure 102 is formed in a substrate 100. A doped polysilicon layer (not shown) is formed over the substrate 100. The doped polysilicon layer is patterned to form a bottom electrode 104 of a capacitor (shown in FIG. 1D) on the isolation structure 102.
In FIG. 1B, a gate oxide layer (not shown) is formed by thermal oxidation. The thickness of the gate oxide layer is about 95 angstroms. A photoresist layer is formed on the gate oxide layer. An etching step is performed to pattern the gate oxide layer. The photoresist layer is removed. A gate oxide layer 106 under the photoresist layer is exposed. The gate oxide layer 106 is used for forming a thick gate oxide layer (shown in FIG. 1C in the following step. However, the photoresist layer may not be completely removed. The device quality is thus degraded.
In FIG. 1C, a thermal step is performed. The gate oxide layer 106 is oxidized again to form a thick gate oxide layer 106a. The thickness of the gate oxide layer 106a is about 125 angstroms. The exposed substrate 100 is also oxidized to form a thin gate oxide layer 116 with a thickness of about 65 angstroms. Because the material of the bottom electrode 104 is doped polysilicon, an oxide layer 126 is formed on the bottom electrode during oxidation. The oxide layer 126 serves as a dielectric layer of a capacitor. However, as it is seen in the above description, the thick gate oxide layer 106a is formed after the double oxidation steps. Therefore, it is difficult to control the thickness of the thick gate oxide layer 106a, and thus device quality is degraded.
A conductive layer 114 is formed over the substrate 100 to cover the thick gate oxide layer 106a, the thin gate oxide layer 116, and the bottom electrode 104.
In FIG. 1D, a conventional photolithographic process is performed to pattern the conductive layer 114. A gate electrode 114a is formed on the thick gate oxide layer 106a and a g,ate electrode 114c is formed on the thin gate oxide layer 116, such that different electrodes with different operation voltages are formed. A top electrode 114b is also formed on the oxide layer 126. Because the conductive layer 114 beside the bottom electrode 104 is thicker than it is on the other regions, it is difficult to completely remove the undesired conductive layer 114 near the bottom electrode 104. The remaining portions of the undesired conductive layer causes current leakage and bridging between the top electrode 114 and the bottom electrode 104.